The LC89091JA digital audio interface receiver is almost certainly part of the ARC/eARC chain as well. And if I had to guess, the iCE5LP4K FPGA is on IR receive/CEC duties.

The only stated differences in video playback capabilities between the 1st and 2nd generation Apple TV 4K models are explicit support for HLG and 60 fps HDR playback at up to 3840 x 2160 resolution, which are likely enabled by the improved video codecs present in the newer A12 SoC. However, the continued use of the MCDP2920 means 4:2:2 chroma subsampling is still required for 4K HDR output at 60 fps.

Apple says this about the HDMI capabilities of the new Apple TV 4K:

“HDMI 2.1*

*Support for up to 4K 60-fps HDR video output and Audio Return Channel (ARC or eARC) only. Requires HDCP when playing protected content and compatible TV or Receiver”

So in this case, the SiI9437 eARC receiver is providing the sole HDMI 2.1 feature supported by this device. HDCP is an entirely separate specification, and AFAIK, Apple has never said that the new Apple TV 4K supports anything beyond HDCP 2.2.

Incidentally, this device and the previous Apple TV 4K both use the Megachips MCDP2920 (not the MCDP2900). I’m not aware of any publicly available datasheets for the MCDP2920, but it is almost certainly a similar DisplayPort 1.4 to HDMI 2.0b protocol converter with HDCP 2.2 repeater. The DisplayPort output of the A12 is routed to the MCDP2920 and the Sil9437 sits on HDMI pins 14 and 19 to perform ARC/eARC duties.

Version 2.1 of the HDMI specification supersedes and replaces version 2.0b. All of the new features in the 2.1 release are optional. This is the same scenario as USB 3.0 > 3.1 > 3.2. To quote the HDMI Licensing Administrator:

“Since each version of the HDMI specification provides a set of potential capabilities and not a set of required functionality… [y]ou shall reference HDMI Specification version numbers only when clearly associating the version number with a feature or function as defined in that version of the HDMI Specification. You shall not use version numbers by themselves to define your product or component capabilities or the functionality of the HDMI interface… If you use an HDMI Specification version number to describe your HDMI implementation, you shall clearly and explicitly identify some or all features or functions of that version of the HDMI Specification that are supported by your implementation.”

Out of curiosity, why do iFixit teardowns always state that the Apple SoC die is “layered over” the SDRAM die(s)? Isn’t the SDRAM always on top in a PoP configuration?

Upon further consideration, I’m pretty sure USB 2.0 never touches the Thunderbolt controllers. In a host setup, the signals are routed from the PCH to each Thunderbolt port controller. In 2-port device configurations, USB 2.0 is routed directly from the upstream port controller to the downstream port controller, unless the design requires USB 2.0 for some reason, in which case it’s routed to the upstream facing port of a hub instead.

As for JHL7440 support for USB3 hosts, the simplest way to achieve this logically is for the downstream Thunderbolt and dedicated USB ports to be connected to the downstream facing ports of a hub, with the upstream facing port of the hub connected to a 2:1 mux which can switch between the upstream Thunderbolt port and the integrated xHCI depending on the capabilities of the attached host. There is probably only a single stepping of Titan Ridge silicon, but for obvious reasons, that mux would have to be either fused off or fixed in firmware for host implementations.

The decision not to include an EHCI in Thunderbolt 3 host controllers is slightly baffling to me, but does make a modicum of sense at least in the host context. I’ve yet to determine whether the JHL7440 includes one, but if it doesn’t, then it’s a pretty ridiculous thing to leave out. You should be able to look at the USB Device Tree in System Information with a USB 2.0 device plugged into the various ports and see how it’s listed. For instance, If I connect a USB 2.0 device to the Thunderbolt 3 port of my MacBook Pro, it shows up under AppleUSBXHCISPT, which would be the Sunrise Point PCH, vs. AppleUSBXHCIAR for Alpine Ridge or AppleUSBXHCIFL1100 for Fresco Logic FL1100. There are very few two-port Titan Ridge devices in the wild where the second Thunderbolt port is actually exposed, and it may be partly due to the shenanigans involved in properly supporting USB protocols on that second port.

Yeah, but you only have a DMI 3.0 x4 uplink to the CPU, which is being oversubscribed to the tune of 2.7:1 or something like that. And the SSD controller in the T2 is perfectly capable of saturating that link all on its own.

Bluetooth module probably has a UART interface, but I can’t recall ever seeing this type of I/O bridge in previous Apple designs.

The conventional PCIe portion of slot 8 sure looks like it’s x8 both physically and electrically, yet we know that’s only billed as an x4 slot. What’s up with that? I’d really like to see better shots of the Apple I/O card.

So now you have me thinking, the C621 PCH only provides 14 USB 2.0 ports, and by my count:

2 for the Thunderbolt 3 ports on the top of the case

1 for the internal USB 3.0 Type-A port

2 for the Thunderbolt 3 ports on the Apple I/O card

2 for the USB 3.0 Type-A ports on the Apple I/O card

4 for MPX slot 1 (up to 4 Thunderbolt 3 ports)

4 for MPX slot 2 (up to 4 Thunderbolt 3 ports)

Which is one too many for the PCH, so there must be a hub or additional USB 2.0 EHCI somewhere to make that work.

I did spy a pair of TI TUSB1002A USB 3.2 10 Gbit/s dual-channel linear redrivers on the I/O card, which would be for the USB 3.0 signals routed from the PCH to the USB Type-A ports via the proprietary portion of the I/O card connector. There’s also the JHL7540, a pair of TI CD3217B or similar USB PD/Type-C port controllers, and possibly a Cirrus Logic CS42L83 audio codec on the card, but you can’t make out any of the part numbers. The audio codec probably needs a couple S2I connections to the T2 chip.